The semiconductor industry is going through a tectonic shift as new end-user applications—especially AI-enabled applications—demand unprecedented levels of compute performance and efficiency. To succeed in this new climate, manufacturers need better tools to manage design complexity and facilitate the integration of third-party IP.
As systems have become more sophisticated, the use of third-party IP has grown tremendously. Despite the fact that the IP is pre-verified, system developers often struggle during IP integration, largely due to problems that occur at the interfaces.
To address this problem, SoCBuilder includes a rich catalog of pre-integrated IP from NetSpeed partners and pre-verified reference designs to ensure easy integration for customers who use any of NetSpeed’s interconnect solutions.
SocBuilder's intelligent design platform equips architects to build custom SoCs for any market segment with ease.
Jumpstart your designs by drawing from built-in reference designs and a rich IP catalog that delivers a wide range of pre-integrated critical SoC IP. SoCBuillder makes SoC development faster and easier, reducing the time to assemble systems to days instead of weeks and months.
Work more efficiently with a unified design environment for IP, chassis integration, design and verification. The system uses meta-data to capture the SoC specification and design details including basic floorplan information and automates much of the design process. SoCBuilder uses machine learning to help find optimum design solutions. A formal construction engine ensures a first-time-right solution.
Harnesses the power of artificial intelligence to achieve the extreme SoC performance next-gen applications need. The platform uses machine learning, advanced networking algorithms and graph theory to solve common design challenges such as cache coherency and QoS and to eliminate conflicts between subsystems, including deadlocks.
SoCBuilder's platform is constructed to produce deadlock free SoC designs. NetSpeed IP uses a graph theory-based approach and formal techniques to ensure that there are no cyclical loops in the entire message dependency chain of the system, thereby ensuring a deadlock-free design.
Architected and designed to reduce wiring congestion and achieve timing closure the first time.
The traditional way of designing interconnect fabric is with a Visio-like approach followed by a disconnected backend implementation process. NetSpeed's interconnect solutions tackle the challenges of SoC interconnect design in a physically aware method.
NetSpeed's interconnect solutions packetize data for on-chip communication reducing the number of wires by 50%. The system optimizes every buffer in the design. The net result is reduced physical congestion paving way for easy place-and-route.
Being physically aware ensures that wiring congestion does not occur late in the design cycle and the appropriate number of buffers and pipeline stages are present at various fabric channels to enable smooth backend design.
SoCBuilder extends the capabilities of NocStudio, NetSpeed’s SoC development platform. Harnessing the power of AI, NocStudio delivers the extreme performance next-gen applications need. NocStudio includes tools that enable architects to design, configure and simulate their SoC designs.
Offers an extensive catalog of pre-integrated IP drawn from NetSpeed's portfolio and ecosystem partners.
Offers pre-verified SoC reference designs for a range of market segments, giving architects a practical starting point.
Work more efficiently with a unified design environment for IP, chassis integration, design and verification. The system uses meta-data to capture the SoC specification and design details including basic floorplan information and automates much of the design process.
Uses machine learning, advanced networking algorithms and graph theory to solve common design challenges such as cache coherency and QoS and to eliminate conflicts between subsystems, including deadlocks. SoCBuilder applies machine learning to find optimum design solutions.
A formal construction engine ensures a first-time-right solution.
Adapts to floorplan and uses placement information to automate timing closure and thus creates a design that is ready for first-pass timing closure.
Plug-n-play of IPs enables easy deployment of core and derivative solutions
Being physically aware ensures that wiring congestions does not occur late in the design cycle and the appropriate number of buffers and pipeline stages are present at various fabric channels to enable smooth backend design.
SoC Builder includes a performance simulator that empowers architects to understand the tradeoffs among power, performance, and area with real-time feedback.
Integrated architectural exploration platform simulates various application use-cases and industry benchmarks.
Optimize either memory sub-systems and complete SoC systems using end-to-end bandwidth, latency and power tradeoff metrics.
Powerful data analytics tools that provide insights on the performance and power bottlenecks in the system.
Perform power, performance,area tradeoff analysis with realtime feedback on SoC bandwidth, latency and power.
See what customers are saying about our SoC development platform.
"This is the way SoC design should be done. NetSpeed’s synthesis engine delivers lower latency by optimizing the design for the specific workloads"
"The speed of NocStudio is amazing. Within minutes, I was able to generate NoC from specification. This completely redefined my architecture and opened up my entire design space"
"What took my team 6 months of painstaking excel sheets, we can do that in minutes with NetSpeed’s Interconnect Synthesis Engine - NocStudio"
"NetSpeed method is architecting for physical design. The NoC place-and-routed beautifully and was timing clean the first time"
"Highly flexible configuration tool with many traffic scenarios modeled. It has rich set of enterprise-level RAS features along with performance/design related outputs for architects."
"This is the way interconnect design should be done. NetSpeed’s interconnect synthesis delivers lower latency by optimizing the design for the specific workloads"
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
Crafted @ Lollypop.biz