Requirements driven design flow that synthesizes SoC interconnect and optimizes PPA based on user specifications.
NetSpeed’s advanced interconnect synthesis engine, NocStudio, along with NoC IP bridges the difficult gap between architecture specification and design implementation. While back-end SoC development flows have benefited enormously from automated tools for logic synthesis, intellectual-property (IP) integration, place-and-route floor planning, and silicon verification, the front-end flow has changed relatively little since the 1990s. It is time to bring the benefits of synthesis to front-end design with an intelligent platform that automates the architecture process and identifies optimal design solutions.
NetSpeed’s advanced NoC IP platform bridges the difficult gap between architecture specification and
design implementation. NetSpeed platform brings the benefits of synthesis to front-end design with
an intelligent platform that automates the architecture process and identifies optimal design solutions.
NocStudio finds the best topology based on user specifications. Sophisticated algorithms determine the most efficient mapping and changes topology as architects add new components. Alternatively, architects can specify a particular topology, overriding the tool’s choice.
NocStudio uses a number of machine learning techniques based on unsupervised learning and simulated annealing to optimize link widths and virtual channel allocation. Each channel is independently optimized creating an optimized NoC guaranteeing the lowest interconnect area and power consumption.
NocStudio's adjusts to last minute Engineering Change Order (ECO) changes using sophisticated algorithms. NocStudio offers multiple kinds of ECO capabilities to allow last minute design changes while minimizing the overall change to interconnect and SoC design. These algorithmic optimizations minimizes effort as well as schedule.
NetSpeed IP is constructed to be deadlock free. NocStudio uses graph-theory based approach and formal techniques to ensure that there are no cycles in the entire message dependency chain of the system, thereby ensuring a deadlock-free solution.
Architected and designed to reduce wiring congestion and achieve timing closure the first time.
Traditional way of designing interconnect fabric is with a Visio-like approach followed by a disconnected backend implementation process. NocStudio tackles the challenges of SoC interconnect design in a physically aware method.
Orion packetizes data for on-chip communication reducing number of wires by 50%. It also optimizes every buffer in the design. The net result is reduced physical congestion paving way for easy place-and-route.
Being physically aware ensures that wiring congestions does not occur late in the design cycle and appropriate number of buffers and pipeline stages are present at various fabric channels to enable smooth backend design.
Support for industry standard IP protocols, and custom proprietary protocols.
Robust, configurable end-to-end QoS schemes: Bandwidth allocation, strict non-blocking priority levels, rate limiters.
Up to 32 virtual network support in the NoC; Virtual channels are allocated to ensure QoS, deadlock avoidance and bandwidth intent satisfaction.
Floorplan aware design flow that enables first pass timing clean solution and reduces wiring congestion.
Support for multiple power domains, voltage domains through industry standard power control interface to support management of power state transitions.
Customize every component of the interconnect from IP interface to routers to topology and interface links using NocStudio.
Graph theory based approach and formal techniques to ensure an application level deadlock-free interconnect solution.
Sophisticated multi-tiered security and firewall support.
Integrated performance simulator that empowers architects to understand the tradeoffs among power, performance, and area with real-time feedback.
Integrated architectural exploration platform simulates various application use-cases and industry benchmarks.
Optimize either memory sub-systems and complete SoC systems using end-to-end bandwidth, latency and power tradeoff metrics.
Powerful data analytics tools that provide insights on the performance and power bottlenecks in the system.
Perform power, performance,area tradeoff analysis with realtime feedback on SoC bandwidth, latency and power.
Architected and designed to reduce wiring congestion and achieve timing closure the first time
Deliver Ultra High Performance to Packet Processing Based Networking Designs
Build Robust and Ultra Low Latency Designs that Adapt to Changing Workloads
Create the Wow! User Experience in a Fast Moving Mobile Market
Build Big Data and Hyperscale Storage for Better Performance and Manageability
Generate Vibrant Digital Home, Set Top Box and Next-Gen Gaming Consoles
Accelerate Advanced Automotive Systems with Reliable Fault Tolterant Designs
Create the Next Generation of Ultra Low Power IoT Retail and Industrial Devices
Create Reference Platforms and Custom Designs Across Market Segments Rapidly
Learn more about our customer’s experience with our technology
"This is the way SoC design should be done. NetSpeed’s synthesis engine delivers lower latency by optimizing the design for the specific workloads"
"What took my team 6 months of painstaking excel sheets, we can do that in minutes with NetSpeed’s Interconnect Synthesis Engine - NocStudio"
"NetSpeed method is architecting for physical design. The NoC place-and-routed beautifully and was timing clean the first time"
"The speed of NocStudio is amazing. Within minutes, I was able to generate NoC from specification. This completely redefined my architecture and opened up my entire design space"
"Gemini has comprehensive feature set that meets my safety, security and reliability needs for Automotive market."
"Highly flexible configuration tool with many traffic scenarios modeled. It has rich set of enterprise-level RAS features along with performance/design related outputs for architects."
"This is the way interconnect design should be done. NetSpeed’s interconnect synthesis delivers lower latency by optimizing the design for the specific workloads"
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
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