NetSpeed Systems Inc. announced today a collaboration with Cadence Design Systems, Inc. that is intended to provide highly optimized and validated interconnect IP solutions for customers developing advanced system-on-chips (SoCs) for AI and autonomous driving applications. The Cadence Interconnect Validator and Interconnect Workbench can enable performance analysis for NetSpeed IP cache coherency features, giving customers a faster and easier way to configure their IP and optimize their SoCs to meet performance requirements.
As advanced driver assistance systems (ADAS) technology matures, manufacturers are extending their focus beyond sensor technology and looking to bring more artificial intelligence (AI) capability onboard. There is a growing realization that key AI functions need to reside on the vehicle platform. This is because it is too risky to have to depend on the availability of a network connection and uninterrupted access to services on the cloud for mission-critical capabilities.
“The development of advanced driver-assistance systems puts intense pressure on designers to meet the increasing demand for high-performance in-vehicle computation,” said Mike Demler, senior analyst at the Linley Group. “To meet these requirements, emerging SoC designs must combine real-time processing with machine learning accelerators running complex AI algorithms, which requires the implementation of high-performance heterogeneous architectures.”
“The problem is that heterogeneous platform designs are far more complex than multicore implementations due to the need to balance diverse processing and traffic needs,” said Sundari Mitra, NetSpeed’s CEO. “At NetSpeed we are using algorithmic methods and applying machine learning technology to make the problem much more manageable for the architect by offering them the best interconnect solutions to choose from. By partnering with Cadence, we are making it much easier and faster for customers to verify their solutions.”
“In our experience, customers designing SoCs for the automotive segment are often looking for a plug-and-play, system-level verification solution,” said Michal Siwinski, vice president of product management and operations, System & Verification Group at Cadence. “As many of these customers are already using the NetSpeed interconnect with the Cadence Interconnect Workbench, a part of the Cadence Verification Suite, we partnered to deliver a joint solution that enables our mutual customers to effectively optimize their SoCs.”
NetSpeed offers a programmable and highly configurable, cache-coherent IP that enables SoC architects to create custom interconnect solutions that achieve the ultimate performance for their heterogeneous designs. Cadence offers its Interconnect Workbench, a tool that automatically generates a Universal Verification Methodology (UVM) environment, providing functional coverage and offering a cycle-accurate performance analysis of interconnect throughout the SoC.
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
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