The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes.Anush Mohandass, vice president of marketing and business development at NetSpeed Systems, discusses how heterogeneity is driving new ways of thinking about SoC design, in this Semiconductor Engineering article: https://semiengineering.com/more-nodes-new-problems/Anush: “An emerging trend here is the concept of a multi-layer chip where the base layer, which may contain the I/Os and some peripheral devices actually existing in 28nm, and then all the different computes, all the things that you’re pushing performance for actually exists on a separate layer. Perhaps that’s on 16nm or 7nm. Although it may be referred to in different ways, it needs some form of intelligence connecting it all together.”
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
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