We are living in the mobile-first era where every mobile device, from a high-end tablets to entry-level smartphones, are at the center of the universe and shaping our lives. Mobile SoC designs are faced with a number of challenges.
Today's mobile SoCs are using an increasing number of processor cores, memory, I/O subsystems, and specialized acceleration IPs on a single die. With growing popularity of design reuse and availability of standardized IPs for SoC design, this trend is accelerating.
Advanced compute architectures such as HSA are bringing compelling new features to the next generation of mobile devices. Third-person gaming, video editing, image recognition and augmented reality are now possible on mobile devices. These sophisticated end-usage applications of the modern mobile SoCs are presenting complex requirements on system Quality-of-Service (QoS) and system bandwidth and latency
Even with the increasing sophistication of these mobile devices, the power requirements have also exploded. Consumers expect and demand phones that go days without charging batteries. This shrinking power envelope is requiring a whole new paradigm shift in designer's approach to power management
The refresh cycles of smart phones, tablets and phablets are shrinking year-over-year. This results in compressed project cycles that require faster design time with new levels of automation
NetSpeed’s advanced NoC IP platform bridges the difficult gap between architecture specification and design implementation. NetSpeed platform brings the benefits of synthesis to front-end design.
NetSpeed has industry’s first and only interconnect synthesis engine to optimize PPA. NocStudio includes tools that enable architects to design, configure and simulate NetSpeed IP as well as evaluate multiple SoC architectures.
NetSpeed platform is a requirements driven design flow that synthesizes SoC interconnect and optimizes PPA based on user specifications. The fabric itself can be designed and customized based on fine-grained user requirements and inputs.
NetSpeed's technology adapts to floorplan and uses placement information to automate timing closure and thus creates a design that is ready for first-pass timing closure.
NetSpeed is relentlessly focused on giving customers industry’s best PPA (Power, Performance, Area). With its unique heterogeneous architecture, NetSpeed’s NoC platform delivers scalable high performance and can support an ever increasing number of IP blocks in a SoC. NetSpeed’s technology uses a physically distributed architecture that enables architects to get the best-in-class performance from the coherent and non-coherent interconnect.
NetSpeed’s NoC platform enables an organization to reduce project risks at every stage in the design cycle.
NetSpeed technology creates application-level deadlock-free interconnects. It uses a graph theory-based approach and formal techniques to ensure full deadlock avoidance both at the network & protocol-level.
NetSpeed IP is aware of the physical layout of the on-chip system components producing an interconnect topology that is customized for the SoC layout.
NetSpeed offers multiple kinds of algorithmic ECO capabilities to allow last minute design changes while minimizing the overall change to interconnect and SoC design. These algorithmic optimizations minimizes effort as well as schedule.
Learn more about our customer’s experience with our technology
"NetSpeed method is architecting for physical design. The NoC place-and-routed beautifully and was timing clean the first time"
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
Crafted @ Lollypop.biz