Hyper-scale platforms such as Facebook and Google, as well as service providers and large enterprises share a common goal to cut energy costs and make better use of power in their data centers. Data center SoC designs are faced with a number of challenges to meet cost, performance, and reliability requirements.
The widespread adoption of cloud computing with its underlying virtualized server technology is driving the use of large numbers of smaller, more power-efficient processors for the jobs running on these servers. This is because virtualization inherently divides the jobs into tasks. Thus, today's data center SoCs are using an increasing number of processor cores, memory, I/O subsystems, and specialized acceleration IPs on a single die.
The limiting factor in data centers is the amount of power available in the building and, in turn, how efficiently the energy and generated heat can be managed. Low-power chip solutions are therefore increasingly in demand.
Cloud computing enables new workloads including big-data mining, machine learning, and Infrastructure as a Service and Platform as a Service offerings. Next-generation server chips will need to offer high-density computing power with hundreds of cores handling many relatively light workloads in parallel.
Data Center dedicated SoCs are some of the best performing chips on the market and are expected to offer 60% more bandwidth every year while decreasing the latency.
NetSpeed’s advanced NoC IP platform bridges the difficult gap between architecture specification and design implementation. NetSpeed platform brings the benefits of synthesis to front-end design with an intelligent platform that automates the architecture process and identifies optimal design solutions.
NetSpeed has the industry’s first and only interconnect synthesis engine to optimize PPA. NocStudio includes tools that enable architects to design, configure and simulate NetSpeed IP as well as evaluate multiple SoC architectures.
NetSpeed platform takes detailed workload information and uses machine learning algorithms to identify the ideal topology needed while solving complex SoC.The fabric itself can be designed and customized based on fine-grained user requirements and inputs.
NetSpeed's technology adapts to floorplan and uses placement information to automate timing closure and thus creates a design that is ready for first-pass timing closure.
NetSpeed is relentlessly focused on giving customers industry’s best PPA. With its unique heterogeneous architecture, NetSpeed’s NoC platform delivers scalable high performance and can support an ever increasing number of IP blocks in a SoC. NetSpeed’s technology uses a physically distributed architecture that enables architects to get the best-in-class performance from the coherent and non-coherent interconnect.
NetSpeed’s NoC platform enables an organization to reduce project risks at every stage in the design cycle.
NetSpeed technology creates application-level deadlock-free interconnects. It uses a graph theory-based approach and formal techniques to ensure full deadlock avoidance both at the network & protocol-level.
NetSpeed IP is aware of the physical layout of the on-chip system components producing an interconnect topology that is customized for the SoC layout.
NetSpeed offers multiple kinds of algorithmic ECO capabilities to allow last minute design changes while minimizing the overall change to interconnect and SoC design. These algorithmic optimizations minimizes effort as well as schedule.
Learn more about our customer’s experience with our technology
"This is the way interconnect design should be done. NetSpeed’s interconnect synthesis delivers lower latency by optimizing the design for the specific workloads"
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
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