One of the difficulties posed by Moore’s Law is that raising the number of transistors on a chip can increase the design time. To combat this effect, designers often reuse intellectual-property (IP) blocks, such as a CPU or DSP core. These IP blocks may be in-house designs proven in an earlier product, or they may be licensed from an IP vendor that has pretested the component; in either case, however, they need not be redesigned or revalidated.
Problems, however, often crop up when connecting these proven blocks to form a complete system-on-a-chip (SoC), particularly as the number of IP cores per chip continues to grow. A poorly designed interconnect is often undersized in some places and oversized in others, and it may have functional errors as well. Finding these errors can take months, extending the time before tapeout. Errors found after tapeout can cost millions of dollars for a new mask set. These challenges are slowing the pace of innovation in SoC design.
Sundari Mitra cofounded NetSpeed Systems in 2011 to help solve this problem. She determined that the solution is to give the designer more visibility as early in the process as possible. In this exclusive interview, she explains where she got the idea and how it improves the design process. For example, she tells this story: “I went to TSMC and asked one of the executives, ‘How is it going for the guys in China?’ He says, ‘Man, are we in trouble. Because they tell us that all the IPs are proven, but we slap it together and the chip doesn’t work!’ Why doesn’t it work? Because the bugs happen in the interfaces. So if you can build it algorithmically, look at the market that becomes available. But to teach people what we have is not easy.”