NetSpeed Systems Inc., the supplier of on-chip network IP that revolutionizes the design of systems on chip (SoC), will introduce the company with a series of presentations at the 2014 Design Automation Conference (DAC). NetSpeed has developed technology that enables SoC architects to design, configure and simulate on-chip networking solutions that are significantly smaller, faster and more power efficient in a fraction of the time normally required. The company’s products bring a new level of automation and intelligence to the design and implementation of the on-chip communication networks. They provide a SoC design platform that streamlines the process of interconnecting the numerous IP cores and subsystems that make up today’s sophisticated SoCs.
“We’ve reached a point at which the complexities of SoC infrastructure can no longer be solved effectively at the IP level alone,” said Sundari Mitra co-founder and CEO at NetSpeed. “Instead we need to be using a new design and planning methodology. NetSpeed wants to bring the power of synthesis to SoC design.”
“The complex SoC architectures required by today’s increasingly sophisticated applications need an interconnect IP solution that is not only robust, but that is also scalable, adaptable and verifiable,” said Richard Wawrzyniak, Senior Market Analyst at Semico Research. “More and more, that means moving to an on-chip network architecture. It is exciting to see a new player in the space like NetSpeed, who brings new thinking to tough challenges.”
SoCs in mobile, automotive, high-performance computing and networking applications evolve rapidly, adding vast new capabilities at every generation. Meanwhile, the methodology and tools for designing and developing complex SoCs have not kept pace, and in some cases SoC architects need to use spreadsheets and general purpose drawing programs to track designs. Once a design is handed off for development, architects have little visibility into the process. It is not uncommon for a design to fail to meet specification on the first try. The process involves trial and error with multiple iterations, thus adding to the risks and delays that are common in SoC development today.
NetSpeed aims to change all this. Founded in 2011 by Sundari Mitra and Sailesh Kumar, NetSpeed is backed by top-tier investors in Silicon Valley. Ms. Mitra previously founded Prism Circuits which was acquired by MoSys. Dr. Kumar, the company’s CTO, previous held Chief Architect positions at Huawei and Cisco. NetSpeed hopes to revolutionize the way SoCs are developed. NocStudio, NetSpeed’s SoC architecture exploration platform offers SoC designers powerful analysis and simulation tools that let them explore potential design solutions and predict potential outcomes at various stages of the development process. NocStudio works in conjunction with the company’s two families of advanced on-chip network IP cores, Orion and Gemini. These products deliver scalable, high performance on-chip network solutions.
NetSpeed will be at DAC 2014, June 2-4 in San Francisco, exhibiting in the ARM Connected Community Pavilion, Booth #2001. Please join us for the following presentations:
About NetSpeed Systems, Inc.
NetSpeed Systems provides scalable, coherent, on-chip network IPs to SoC designers for a wide range of markets from mobile to high-performance computing and networking. NetSpeed's on-chip network platform delivers significant time-to-market advantages through a system-level approach, a high level of user-driven automation and state-of-the-art algorithms. NetSpeed Systems was founded in 2011 and is led by seasoned executives from the semiconductor and networking industries. The company is funded by top-tier investors from Silicon Valley. It is based in San Jose, California and has additional research and development facilities in Asia.
We’ve reached a point at which the complexities of SoC infrastructure can no longer be solved effectively at the IP level alone,” said Sundari Mitra co-founder and CEO at NetSpeed. “Instead we need to be using a new design and planning methodology.