Partitioning Becomes More Difficult

  • Ann Steffora Mutschler, 30th Apr 2018

The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow.

Anush Mohandass, Netspeed's VP of marketing and business development, discusses his experience with this problem, in this Semiconductor Engineering article:

Anush: “With lower nodes, engineering teams are partitioning the entire system and essentially saying, ‘I’m going to have two separate chips, one for my main high-performance engines, and the second for my low-performance engine that doesn’t quite need to be produced over and over again.' There is also an interconnect between them. This is a problem engineering teams are faced with when they have to emulate their design using an FPGA. FPGAs are great for ASIC emulation. You don’t need to necessarily burn millions of dollars to understand whether your system is performing, whether you have any functional bugs, or whether you have any performance bugs. But the difficulty is mapping the entire SoC onto a single FPGA. Therefore it is partitioned into multiple FPGAs.”

Request A Demo


Crafted @