One of NetSpeed’s customers is a Tier-1 semiconductor company that develops some of the industry’s best performing and most complex system on chips (SoC) for the data center and cloud computing markets. To keep its leadership in the data center market, the company needs to produce best-in-class SoC solutions year after year. Today, NetSpeed’s Network-on-Chip (NoC) is at the heart of these super-SoCs.
The main challenge for the data center market can be summed up in a few words: offering 60% more bandwidth every year while decreasing the latency. Adding more servers can’t be the only solution because that would severely impact latency. Even if existing designs achieve best-in-class latency, future SoC generations will require even lower latency. Moreover, with in-memory computing replacing previously used storage solutions like hard disk drives, traditional latencies have to be greatly reduced to enable real-time, data-driven decision making.
This customer used to hand-tune interconnect designs and it was severely impacting the design and verification schedule and requiring chip architecture iterations, as the methodology for deadlock discovery, analysis and resolution added an extra 6 months to the development schedule. Therefore, a solution that was guaranteed to be deadlock-free could save up to 6 months of development time and generate a huge time to market advantage.
Not all interconnects (or NoCs) are created equal. NetSpeed provided an interconnect synthesis engine, an innovative solution that optimizes the interconnect architecture based on workload models. Implementation of NetSpeed’s NoC led to a new generation SoC that delivers 25% lower latency and 29% higher maximum frequency than previous ICs. Because NetSpeed synthesizes a pre-verified interconnect design within minutes, the direct impact on design schedule is to shrink six months of analysis down to a few hours.
Data center dedicated SoCs are known to be the best-performing ICs on the market. NetSpeed’s NoCs enabled a new generation SoC that delivers 25% lower latency and 29% higher maximum frequency than previous ICs. But the SoC optimization effort to reduce both area and power consumption has to be pushed to the maximum in order to create a power conscious solution leading to an economically viable chip size.
Both power consumption and area are directly impacted by the number of wires and buffers in the SoC interconnect. NetSpeed’s interconnects can be optimized to reduce the number of wires and buffers. This created an SoC design that offers higher performance than previous generations while reducing area by 40%, wire count by 26%, and buffer count by 46%.
Using NetSpeed’ NoC solution is probably not enough to magically solve the data center power consumption issue forever. Offering 40% lower power than previous generation is already a great achievement and saving 6 months on the SoC design schedule can allow reassigning creative and experienced people like SoC architects and designers to other tasks. For example, they could rework and optimize the architecture of the data center itself to create future storage and processing units that could become so power friendly that you don’t need to submerge the data center…
This blog is extracted from NetSpeed “Data Center” Success Stories. You can read more about this story and Mobile AP, Automotive SoC, Networking, Digital Home SoC or Data Center Storage stories HERE.
From Eric Esteve from IPNEST