Why Gemini 2.0 is tailored for tomorrow’ SoC designs?

  • By Eric Esteve
  • 4th Nov 2015
  • 10
You probably have seen many times this graphic showing that the number of IP blocks has exploded, going from a few dozens in SoC designed in 65 nm to 120 if not more for last generation SoC targeting 16FF or 10FF. This graphic is very good at synthesizing the raw IP count, but it doesn’t tell you about another strong trend: more agents are participating in coherency. We may turn this another way: complex SoC designs are moving from homogeneous zone of comfort to heterogeneous, and this reality has started as soon as designs have moved to single core (single cache level) to TWO cores supporting cache memory. Looking at the picture below, you realize that certain designs may integrate several very complex multi-CPU (and GPU) clusters, architectured around three cache levels. Cache coherency is becoming a key issue, when integrating a Network-on-Chip, better to make sure that the NoC is cache coherent!


NetSpeed has initially built Gemini NoC IP to explicitly support cache-coherent designs, the new version, Gemini 2.0, has been developed to support SoC requiring coherency across multiple IP clusters. Customers are using NoCStudio to create ARM compliant interconnects using AMBA-compliant, ACE and ACE-lite, as well as coherency details. Gemini 2.0 improves configurability, adding a last level cache option and generates synthesizable RTL. Gemini 2.0 is an automated coherent NoC generator and the design team will take benefit of the tool, especially when being under the pressure of an aggressive schedule.


A new feature has been added into Gemini 2.0, Pegasus cache. In fact, Pegasus is a configurable IP and the designer will determine cache capacity, associativity, banking, internal power gating and allocation policies for each Pegasus, as a SoC can include several Pegasus modules. For example, the number of outstanding cache misses and other cache configuration features are configurable.

Using NetSpeed coherent NoC architecture allows improving cache utilization by controlling address ranges serviced by each cache, or defining which IP blocks can access the cache. A coherent cache only allows coherent access. What about the non-coherent traffic? It goes directly to memory.


Pegasus only supports one layer of coherency, and if different IP blocks including the same Pegasus cache, they will be non-coherent to each other. NetSpeed NocStudio enables cache hierarchy customization. Gemini 2.0 architecture is flexible enough to adapt to different scenario. Clearly explained on the above picture, different clusters made of two CPU with cache can be implemented in a variety of manners. One cluster will require the two CPU to share the same Cache Coherency Controller (CCC), the same Last Level Cache and the same (external) memory. Another cluster will be architecture with CPU still sharing the same CCC, but one CPU directly accessing on-chip RAM when the other will access external memory through Last Level cache…

Such greater flexibility explains why customers developing complexes coherent systems would greatly benefit from Gemini 2.0 to accelerate Time-To-Market. Architects who need a scalable, high-performance, correct-by-construction SoC interconnect should evaluate NetSpeed's technology, especially if the design requires cache coherence.

 

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