When you look at NetSpeed’s NocStudio design tool, you first think “I see, NetSpeed is a new Network-on-Chip (NoC) IP company”. Are you wrong? Yes and no… No because NocStudio indeed generates a NoC. Yes, because the company objectives are going much farther than simply deliver a new NoC solution. According with Sundari Mitra, CEO and founder of NetSpeed, she has decided to launch this start-up to address an issue that architect and design teams are facing for decades, how to bridge the gap between architecture and Tape out? Sundari consider that NocStudio is “correct by construction”, addressing SoC synthesis. It’s a high level tool (higher than RTL synthesis), the idea is to bring the power of synthesis to SoC design. How does it work? Sundari answers this question: “This is an algorithmic solution to how SOC should be put together. It is all based on mathematics graph theory and networking algorithms to optimize what is done on a SOC. If you look at the tag line, it doesn't say that we are a NOC company, it says we are redefining how SOCs should be designed.”
Before trying to understand NocStudio itself, it’s interesting to look at the background of NetSpeed technical team. At first Sundari: she has started working with Intel long time ago (on the nMOS 286) and since then has participated to dozens of SoC TO, facing last time issue like finding deadlocks, just before TO if you are lucky… and sometime after TO. Another point, Sundari was one of the founders of Prism Circuits, a start-up developing High Speed SerDes IP which has been acquired by MoSys in 2009 for $20M (the same price than Snowbush in 2007, but Prism Circuits was much younger).
Because NocStudio is based on the same type of algorithms than these used in Networking, one of the cofounders is a brilliant guy called Sailesh Kumar, who has worked in Cisco advanced research, Huawei, and comes from a strong networking background. It was clear from the beginning that NocStudio had to address cache coherent SoC designs and that’s the reason why Joe Rowland has join the team (Joe currently holds 80 patents on cache coherency and memory sub-system design).
The team has designed NocStudio as a graphical tool helping automate a SoC design using optimal-path algorithms adapted from computer networking and telecommunications. Architect will drop IP blocks into the left window and NocStudio will generates the links between the various IP as well as the script that defines the IP blocks for the synthesis compiler. NocStudio is not a place and route of floor-planning tool, but can be said as “floorplan aware”. To minimize interconnects between the various IP blocks, you need to know where these will be placed in the real SoC design. For architects who prefer working on scripts, the tool generates a script that you can edit and modify in a third window, synchronized with the graphic tool.
That’s great, but is NocStudio really efficient?
On the above figure we can see the chip optimization on a real life example, step by step: placement, layers, routing and channels optimization allows generating an optimized SoC. Not only the wire length and buffer count has been optimized, leading to a much easier place & route phase, but the final SoC is said dissipating 60% less power than with AMBA AXI interconnects.
So NocStudio is at first a front end optimization design tool and Sundari claims that such tools will become unavoidable for today’s SoC designs, like was software compiler and RTL synthesis before.
Sooner or later, the industry will embrace front-end design tools that inevitably will look very much like NocStudio. Architects who need a scalable, high-performance, correct-by-construction SoC interconnect should evaluate NetSpeed's technology, especially if the design requires cache coherence.
From Eric Esteve from IPNEST