At NetSpeed, we speak 4 languages: Flexibility, Scalability, Deadlock-free and Physical-awareness in a coherent fashion. We strongly feel, and many customers agreed, that system architect should have the freedom to build any cache hierarchy as they think the best for the application. Gemini does exactly that. By giving customer a fully distributed cache hierarchy solution, Gemini unleashes the physical design constraints and allows SOC blocks to be placed anywhere on the die while still meeting timing at ease with NetSpeed physical-aware synthesis / design capture platform – NocStudio.
Any existing AMBA based SOC with coherency can benefit from Gemini's full configurability. Instead of having a semi-fixed coherency block, Gemini offers 3 flexibly placable components: CCC - Directory based Cache Coherency Controller IP, IOCB - IO Coherent Bridge / Accelerator and DVM - Distributed Virtual Memory. Each component can be instantiated as many times as needed and can be placed at any desirable location. NocStudio synthesis engine can then construct the NoC with Gemini to satsify the requirements cohrently and non-coherently, functionally and physically.
As Gemini is a superset of Orion – NetSpeed non-coherent solution, in addition to the standard non-coherrent AMBA protocols: AXI4, AXI3, AHB, APB, etc., Gemini supports ACE, ACE-Lite and ACE-Lite w/ DVM. Gemini is the industry first single solution to esnure a deadlock free NoC for the entire system.
For starters, a single CCC who can manages all coherency traffic is probably good enough. As complexity increases in modern SOCs, having multiple CCCs can increase the overall coherent bandwidth. Secondly, distributed directory means smaller directory RAM size for each CCC, therefore it will reduce overall system latency due to faster memory access time. Lastly multiple CCCs provides placement flexibility where each CCC can be placed as close as possible to their connecting coherent masters, respectively.
Slaves or targets may have one or more address ranges. A master device may access all or a subset of these address ranges. Furthermore, though a slave address range may be accessible to a master device, it may be disabled, or selectively enabled for reads or writes, or for accesses with secure privilege. The initial register map and access privileges can be set up through NocStudio, but it may be modified in silicon through Regbus programming. Address mapping could be highly interleaving with different granularities.
Yes, Gemini supports speculative read.
No, Gemini does not need to do any dummy snooping. We have a directory based solution that filters unncessary snoops.
Yes, we support partial clock gating under system firmware control or NoC adaptive control.
Yes. Gemini supports transaction splitter for I/O coherent masters.
Yes. Gemini supports WriteUnique in order.
Gemini provides transportation for non-coherent exclusive transactions. It also supports coherent exclusive transactions with tracking address per agent.
For IO coherent transactions, Gemini propagates them through the network whereas for others it waits for the prior transactions to complete.
Yes, Gemini can route coherent and non-coherent accesses to different master ports.
Yes, slave ports could be disabled dynamically.
NetSpeed Gemini supports multiple QoS mechanisms: traffic isolation, strict priority-based and weighted allocations. Additionally, NoC virtual channels are algorithmically optimized to best fit floorplan, connectivity and to reduce power.
NetSpeed Gemini supports multiple performance registers in the NoC. These performance registers are programmable and can be used to measure bandwidth, latency and other notable events at runtime. These performance registers are accessible through a separate physical layer called the “RegBus”.
Yes, NetSpeed Gemini supports multiple performance registers in the NoC. These performance registers are programmable and can be used to measure bandwidth, latency and other notable events at runtime. These performance registers are accessible through a separate physical layer called the “RegBus”.
We provide a comprehensive set of debug mechanism to enable pre-silicon and post-silicon verification and debugging. Some of the capabilities/features include:
Yes, we support both async as well as a 1:N and N:1 clock domain crossing.
External system level clock gating, adaptive coarse grained clock gating (which automatically gates inactive blocks) and fine grained clock gating.
Yes, we will allow insertion of async FIFOs in our router than will enable asynchronous voltage domain crossing bridge as well.
Yes, the NoC can be divided across power domain boundaries. On top of this, Gemini provides a comprehensive Low Power solution. It optimizes power-domain allocation based on SoC level power profiles and power mixes. A demo of NocStudio will be able to demonstrate our sophisticated low-power approach. Please contact us for more details.
Gemini supports ARM Trust Zone controller which gates the memory. In addition, Gemini also provides fine-grained features of secure memory access. With address ranges specified for slave bridges, master bridges could be set up to have restricted access to specific slave address ranges. For Coherent Cache, the “secure/non-secure” protection bit of AXI channels are also used, in conjunction with the cache directories, to ensure secure cache access.
Whether you are a hardware architect looking for cache coherency solutions to realize your ideas into silicon or a SoC designer looking for a high performance and efficient interconnect or a safety manager looking for solutions to build resilient, fault-tolerant systems—NetSpeed has a solution for you.
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