Orion offers system architects a better way to design way to design and optimize SoCs. Starting with high-level system requirement as inputs. Orion uses its built-in interconnect synthesis engine to construct an optimized network-on-chip solution.
NetSpeed's underlying Network-on-chip architecture is geared towards addressing some of the fundamental architecture requirements of Networkings ASICs and SoCs.
NetSpeed's underlying Network-on-chip IP is based on sending packetized data between the routers and exposes the same packetized format to the hosts and processing engines in a Networking ASIC. This eliminates the need for area- expensive bridges and also produces a latency optimized interconnect solution.
NetSpeed's IP uses a number of machine learning techniques to optimize number of design options, from NoC topology to link widths and virtual channel allocation. Sophisticated algorithms determine the most efficient mapping and changes topology as architects add new components. Alternatively, architects can specify a particular topology.
Traditional way of designing interconnect fabric is with a Visio-like logic-block-building approach followed by a disconnected backend implementation process. NetSpeed’s IP is physically aware of the layout of the on-chip system components producing an interconnect topology and IP that is customized for the SoC layout.
NetSpeed technology bridges the difficult gap between architecture specification and design implementation. While back-end SoC development flows have benefited enormously from automated tools for logic synthesis, intellectual-property (IP) integration, place-and-route floor planning, and silicon verification, the front-end flow has changed relatively little since the 1990s. NetSpeed’s IP brings the benefits of synthesis to front-end design with an intelligent and scalable platform that automates the architecture process and identifies optimal design solutions.
NetSpeed NoC platform has advanced analysis tools that allows for fast, accurate simulation without the additional overhead of building complex models of endpoints. Using these tools enables more iterations early in the design process, allowing for better exploration of the solution space and a better design in less time.
NocStudio has an integrated performance simulator with a powerful data analytics tool suite that analyze the traffic specification of a SoC and provides insight on the performance bottlenecks in the system. Architects can perform performance,area tradeoff analysis with realtime feedback.
NetSpeed IP is constructed to be deadlock free. NocStudio uses graph theory based approach and formal techniques to ensure that there are no cycles in the entire message dependency chain of the system, there-by ensuring a deadlock-free solution.
Dynamic performance and use case evaluation is performed using traces and sophisticated trigger graph models. Complex simulations using trigger graphs enable rapid and accurate NoC evaluation in complex systems by allowing fast benchmarking of evolving endpoint behavior and traffic specifications.
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