We are living in the mobile-first era where every mobile device, from a high-end tablets to entry-level smartphones, are at the center of the universe and shaping our lives. Mobile SoC designs are faced with a number of challenges.
NetSpeed’s advanced NoC IP platform bridges the difficult gap between architecture specification and design implementation. NetSpeed platform brings the benefits of synthesis to front-end design.
NetSpeed has industry’s first and only interconnect synthesis engine to optimize PPA. NocStudio includes tools that enable architects to design, configure and simulate NetSpeed IP as well as evaluate multiple SoC architectures.
NetSpeed platform is a requirements driven design flow that synthesizes SoC interconnect and optimizes PPA based on user specifications. The fabric itself can be designed and customized based on fine-grained user requirements and inputs.
NetSpeed's technology adapts to floorplan and uses placement information to automate timing closure and thus creates a design that is ready for first-pass timing closure.
NetSpeed is relentlessly focused on giving customers industry’s best PPA (Power, Performance, Area). With its unique heterogeneous architecture, NetSpeed’s NoC platform delivers scalable high performance and can support an ever increasing number of IP blocks in a SoC. NetSpeed’s technology uses a physically distributed architecture that enables architects to get the best-in-class performance from the coherent and non-coherent interconnect.
NetSpeed’s NoC platform enables an organization to reduce project risks at every stage in the design cycle.
NetSpeed technology creates application-level deadlock-free interconnects. It uses a graph theory-based approach and formal techniques to ensure full deadlock avoidance both at the network & protocol-level.
NetSpeed IP is aware of the physical layout of the on-chip system components producing an interconnect topology that is customized for the SoC layout.
NetSpeed offers multiple kinds of algorithmic ECO capabilities to allow last minute design changes while minimizing the overall change to interconnect and SoC design. These algorithmic optimizations minimizes effort as well as schedule.
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